The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the transistor Q5.
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the transistor Q5.
电平调节电路100将送往第一个时钟终端CK1的时钟信号从H电平降低一个预定值，并将此信号送往晶体管Q5的输入端。