For this design,SPWM waveform data only in one / sinuous cycle are required to be stored in ROM that is constructed with internal hardware resource of the FPGA.
For this design,SPWM waveform data only in one / sinuous cycle are required to be stored in ROM that is constructed with internal hardware resource of the FPGA.
该电路用一片用户可编程门阵列（FPGA）芯片实现，电路设计只需将／周期的SPWM波形数据存于FPGA内部硬件资源所构造的ROM中，因此减少了硬件开销。