Error: VHDL error at shift.vhd(18): can't infer register for signal q[3]because signal does not hold its value outside clock edge.
Error: VHDL error at shift.vhd(18): can't infer register for signal q[3]because signal does not hold its value outside clock edge.
每个时钟上升沿移位一次,按您说的要加循环吧.移位一次没问题,加上循环就不行了,有错误.